3-D Interconnects Using Cu Wafer Bonding : Technology and Applications

3-D interconnects hold tremendous potential to reduce global interconnect latency and power dissipation. Moreover, it allows heterogeneous integration, i.e., monolithic integration of different technologies (e.g., logic, memory, and RF). This paper explores the opportunities and challenges of the 3-D integration approach by low temperature direct Cu-to-Cu wafer bonding. A thorough description of process integration will be given and key technological challenges will be highlighted. In particular, interfacial morphologies of low temperature Cu-to-Cu wafer bonding at 400 C have been characterized structurally. Microstructure examination results show excellent bonding properties. In addition, CAD tools for 3-D IC design and layout are being developed. Potential 3-D applications to system-on-a-chip will be discussed.